Keypad Interfacing With 8051 Pdf' title='Keypad Interfacing With 8051 Pdf' />The PCAM Practical Course for Atmel Microcontrollers is designed for beginners. It includes development hardware with onboard interfaces and an insystem. NTSCHYD PROSPECTUS ON TRAINING PROGRAMS NSICTECHNICAL SERVICES CENTRE, HYDERABAD A Govt. India Enterprise Kushaiguda Electronic Complex, Kamalanagar. Microcontroller PIC Projects are categorized on the basis of microcontroller applications. Microchip pic microcontrollers belongs to modern family of MCUs. Traditional lock systems using mechanical lock and key mechanism are being replaced by new advanced techniques of locking system. These techniques are an i. Rickeys World of Microcontrollers Microprocessors. This project demonstrates a great concept of Home automation using a Smart Home Device which can control things automatically by taking decisions based on sensor network and external events or manual control using your phone over Bluetooth or GSM. Which means if you are inside the house you can use You can control your appliances using bluetooth when outside use your GSM phone over SMS. This project uses AVR controller ATMega. Arduino firmware. There are a number of sensors connected to the controller some on GPIOs and some via Analog ports. Here is a short list of sensors 1. Temperature Sensor LM3. PIR Sensor. 3. Light Sensor LDR4. GAS Sensor. Wireless modules used in this project 1. SIM3. 00 GSM Module SIM9. HC 0. 5 Bluetooth Module. There is also a provision for controlling 4 AC appliances. One LCD is also connected to show real time status of all the sensors. This project gives a good hands on practice on AVR controller and Arduino firmware programming. With various communication options one can get good experience on wireless communication. Further more there are endless possibilities of expanding this project. So you really need to turn your brains on and think of what more you can do with this. Project also includes complete documentation including Synopsis, Project report and final presentation. But dont get carried away with these goodies. Pokemon Type Wild 5.0. Learn and Build this project so it can benefit you in future I really want to thank Gaurav Khadasane once again for submitting this wonderful project and bringing lot of things together to learn in a single project. Go to download section to download this project Smart Home using GSM, Bluetooth and Android. Finally the working Demo. How to use SPI Serial Peripheral Interface in AVR Microcontrollers                Micro controllers support wired communication protocols. Most of the time, microcontrollers come along with internal modules that support these protocols. The commonly supported protocols are UART or USART communication. SPITWIUSI etc. And few advanced protocols like SPI stands for Serial Peripheral Interface and it is the simplest among all the communication protocols. These data registers works as shift registers and one of the device controls the data exchange inside the  SPI Network. The device or devices that controls the operation inside the network is known as the Master. For more elaboration, you may read the Wikipedia article Serial Peripheral Interface Bus. There can be multiple Masters in a system. There may be multiple slaves too. The slave need not to be another micro controller. It can be an SD card, or some display device or may be some other electronic circuit. Irrespective of the device attached as a slave, it needs to get selected by master devices for data transfer. If the system is a multi master  network, then each individual secondary master needs to be selected for mastering the SPI BUS. An SPI bus consist of two DATA lines, one clock line, and device select or slave select lines. The clocking signal is generated by the master in the network. Here, in this experiment, one system is build up to receive any character transmitted in the SPI. And it displays the character on the LCD display. So the receiver circuit is essentially a slave. As the receiver system will never transmit any data, we can keep it enabled all the time. There would be a master device that will transmit a string of character, either once, or repetitively. So lets see, what are the available resources for this communication. Register Description. SPI Status Register SPSRBit. Bit Name. SPIFWCOLSPI2. XReadWrite. RRRRRRRRInitial value. Bit 7 SPIF SPI Interrupt Flag. When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register SPDR. Bit 6 WCOL Write Collision Flag. The WCOL bit is set if the SPI Data Register SPDR is written during a data transfer. The WCOL bit and the SPIF bit are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. Bit 5. 1 Res Reserved Bits. Bit 0 SPI2. X Double SPI Speed Bit. When this bit is written logic one the SPI speed SCK Frequency will be doubled when the SPI is in Master mode. This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at  or lower. SPI Control Register SPCRBit. Bit Name. SPIESPEDORDMSTRCPOLCPHASPR1. SPR0. ReadWrite. RWRWRWRWRWRWRWRWInitial value. Bit 7 SPIE SPI Interrupt Enable. This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the global interrupt enable bit in SREG is set. Bit 6 SPE SPI Enable. When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. Bit 5 DORD Data Order. Bit 4 MSTR MasterSlave Select. This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re enable SPI Master mode. Bit 3 CPOL Clock Polarity. Bit 2 CPHA Clock Phase Bits 1, 0 SPR1, SPR0 SPI Clock Rate Select 1 and 0. These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency  is shown in the following table Relationship Between SCK and the Oscillator Frequency. SPI2. XSPR1. SPR0. SCK Frequency. 00. The SPI Data Register is a ReadWrite Register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. SPI Data Register SPCRBit. MSBLSBReadWrite. RWRWRWRWRWRWRWRWInitial value. XXXXXXXXX Undefined. Points to be Noted. It is to be noted that when SPI is enabled, not all the pin function in the SPI ports are over ridden. Operations differ. Lets have look on the effects. Modes. Master. Secondary master in Multi Master mode. SS Driven LOW Input To SS0Secondary master in Multi Master mode. SS Driven HIGH Input To SS1Slave Mode. Conditions. The MSTR bit in SPCR is set i. MSTR1 the bit in DDR Relevant to SS is set. The MSTR bit in SPCR is set i. MSTR1 the bit in DDR Relevant to SS is reset i. The MSTR bit in SPCR is reset i. MSTR0MOSIThe relevant DDR bit must be set to 1. SPI overrides the pin functionality. MOSI becomes Input. The relevant DDR bit must be set to 1. MOSI becomes Output. SPI overrides the pin functionality and configures the DDR bit to 0. MISOSPI overrides the pin functionality and configures the DDR bit to 0. The relevant DDR bit must be set to 1. MISO Remains Input. The relevant DDR bit must be set to 1. MISO Remains Input. The relevant DDR bit must be set to 1. SCKThe relevant DDR bit must be set to 1. SPI over rides the pin functionality. SCK Becomes Input. The relevant DDR bit must be set to 1. SCK Becomes Output. SPI overrides the pin functionality and configures the DDR bit to 0  Slave selectThe relevant DDR bit must be set to 1. SS is Configured as Input. Input To the SS pin is a logical 0SS is Configured as Input. Input To the SS pin is a logical 1SPI overrides the pin functionality and configures the DDR bit to 0. The clock generator unit is Stopped. DDR Data Direction Register. To Enable SPI operation these simple steps are sufficient                a. SET the SPE bit in SPCR register. SET or RESET the MSTR bit in SPCR register                c. Configure the Data Direction Register DDR of the digital IO port to which the SPI belongs to. Configure it as required                d. Its not necessary to configure the Prescaler bits. SPI exchanges the contents of the SPDR of master and slave. So precautions should be taken so that garbage contents doesnt get transmitted, or used. Circuit Diagram. Refer this PDF file  Working with SPIFig Circuit Diagram. Codesifndef PROJECTHdefine PROJECTHifndef AVRIOHincludelt avrio. UTILDELAYHincludelt delay. STDIOHincludelt stdio. DPDDRdefine DPDDR DDRCendififndef CPDDRdefine CPDDR DDRDendififndef CPORTdefine CPORT PORTDendififndef DPORTdefine DPORT PORTCendififndef RSdefine RS PD2endififndef ENdefine EN PD3endifdefine DEL1 1. DEL2 4. 5int LCDchar ch, FILE fp int LCDchar ch,FILE pDPORTch 4 0x. CPORT1lt delayusDEL1 CPORT1lt delayusDEL1 DPORTch 0x. CPORT1lt delayusDEL1 CPORT1. CPORT0lt delayusDEL1 CPORT0lt delayusDEL1 DPORTch 0x. CPORT0lt delayusDEL1 CPORT0lt delayusDEL2 delayusDEL2 ifch0x.